Delay fault testing of IP-based designs via symbolic path modeling
نویسندگان
چکیده
Delay testing of designs that contain intellectual property (IP) cores is challenging. We propose a method that can test paths traversing both IP cores and user-defined blocks. It employs a highly efficient BDD-based path modeling method and an associated ATPG technique. Experimental results show that it can robustly test selected paths without using extra logic, and protects the intellectual property.
منابع مشابه
Scan Design and AC Test
We propose a novel Design for Testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for detecting stuck-at as well as delay faults quickly and efficiently. Existing techniques such as enhanced scan add substantial hardware overhead, whereas techniques such as s...
متن کاملResynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Reduction and for Path Delay Fault Testability Angela Krsti c and Kwang-Ting (Tim) Cheng Department of ECE, University of California, Santa Barbara, CA 93106 Abstract Path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability o...
متن کاملCritical Paths Selection for Delay Faults
Extended Abstract Right timing of complex digital circuits and systems in nanotechnology need careful design steps and testing. Incorrect timing can be caused during design or manufacturing processes. Incorrect timing is manifested as delay faults. The delay faults in digital circuit testing are more and more important due to huge number of gates and lines integrated on a chip specifically in n...
متن کاملEfficient Path Delay Test Generation for Custom Designs
ETRI Journal, Volume 23, Number 3, September 2001 Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom...
متن کاملSoftware-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition probabilities (profiles) at the inputs of circuits with full-scan using testability metrics based on the targeted fault model. We use a genetic algorithm (GA) based search procedure to determine optimal profiles. We use ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1999